The switch from 14 nm to 12 nm engraving will allow Samsung to produce RAM memory modules that increase in frequency (speed) and are less expensive to produce (more modules per wafer). What accelerate the adoption of a memory which, in a strange way at first sight, is engraved less finely than the last generation of DDR4… Explanations.
While we always welcome new technological developments, we like even more those that bring prices down. Like this announcement by Samsung of the upcoming arrival of new DDR 5 RAM modules engraved in 12 nm. An evolution of the manufacturing process that will, according to Samsung’s promises, allow memory modules to be more energy efficient while being ” up to 23% more efficient » than the current DDR5 modules engraved in 14 nm. What is striking is that a quick glance in the rear view mirror reveals that Samsung has already been delivering DDR 4 at 10 nm since the beginning of 2022. How is it that a memory lively more modern engraved less finely or faster? And why the hell isn’t Samsung dropping straight to its DDR 5 in its thinnest manufacturing node? And what are the announced performances of this new memory?
First the speed…
First of all, let’s clarify that the most important need for memory concerns speed more than the amount of memory. Granted, a very few PC video games are starting to require 32GB of RAM and push graphics needs beyond 12GB, but overall the progress in the amount of memory is slowly moving. PCs cap at 16 GB with a few 32 GB references (excluding professional use), as do smartphones. What all sectors need, however, is an acceleration of the way data flows between the various electronic components of our machines. And there is a real bottleneck: while chips for PCs, smartphones and other supercomputers will continue to see their power increase very significantly from year to year, the speed of memory exchanges (RAM, network) climb much more gently.
Read also: DDR5: the new generation of RAM is finalized and will arrive in PCs in 2021 (July 2020)
This preamble thus makes it possible to explain why the future DDR5 modules of Samsung planned for the 4e quarter of 2023 will be engraved a little more “coarsely” than the previous generation DDR4. Because the main contribution of DDR5 is less the theoretical maximum capacities of the modules (even if it is on the rise) than the way in which the information passes through. Without going into details, DDR5 provides better power management as well as a lower voltage (1.1V against 1.2V) which allows lower consumption at the same frequency – and to tease higher frequencies. Its superior speed is also due to the way it addresses each memory module not on just one, but on two channels, or even four for double-row modules. This allows Samsung to claim that its modules can go up to 7.2 Gbit/s.
… Then control, then finesse
Enthusiasts of fine-etching might ask, “Why the hell doesn’t Samsung etch 4nm memory modules like they do CPUs?” “. Question justified on paper… but not in practice. Because it must be understood that the chips are not engraved engraved in 4 nm: only the calculation parts of the CPUs (see also the GPU part) benefit from this density. In fact, the internal memory elements of processors (a type of memory called SRAM) cannot be compacted as densely as the transistors linked to calculations.
The concern with memory in general is that its spatial conformation – its 3D shape – and its need for isolation between each cell to preserve the integrity of the information limits miniaturization. Since DDR5 derives its quality from greater complexity and yields being the keystone of the profitability of a semiconductor production plant, Samsung must take it step by step. First rely on effective methods, even if all the same at the cutting edge (the previous 14 nm was already in EUV), then push forward with miniaturization. Without ever compromising on quality or yields.
Ultimately, not only will DDR5 join DDR4 in reaching 10 nm of fineness of engraving, but it will become denser: TSMC has already validated 5 nm processes with software giants in chip manufacturing such as Synopsys and Cadence. But these theoretical steps do not proceed from a sufficient yield for immediate commercial exploitation. Once these tools are developed, they need to be integrated into a real-world based workflow. That is, finding the right chemical components, refining the production steps, etc. Which can take years.